1. Field of the Invention
The present invention relates to a BiMIS (Bi-MIS) logic circuit in which bipolar transistors and MIS transistors are combined, and more particularly to a BiCMIS (Bi-CMIS:complementary MIS) static logic circuit, a dynamic logic circuit, and a semiconductor integrated circuit adapted for a super high-speed operation at a low-power supply potential or voltage.
2. Prior Art
A so-called BiCMIS logic circuit using bipolar transistors and CMIS transistors is described in U.S. Pat. Nos. 4,558,234, 4,616,146, 4,638,186, 4,769,561 and others and has been known. The contents of these patents are incorporated in this specification by a reference.
FIG. 27 shows the BiCMIS logic circuit disclosed in U.S. Pat No. 4,769,561 described above. This circuit has an advantage of a low-input-capacitance and high-output driving capability and capable of operating at high speed with low-power dissipation. For this reason, the circuit is used in LSIs requiring a high performance and memories. The circuit can achieve the above-described advantage when the power supply potential or voltage is about 5 V but cannot be operated at high speed when the power supply potential is about 3 V. The deterioration of the high-speed operability with the reduced power supply potential is due to the remarkable increase of delay of a negative-going output signal 2720 with respect to a positive-going input signal 2710, as shown in FIG. 28. FIG. 29 shows a power supply potential dependency of the delay time of the negative-going output signal. In FIG. 29, the solid line and the broken line indicate the power supply dependency of the inverter delay time with respect to the CMIS logic circuit and the BiCMIS logic circuit, respectively. As is apparent from FIG. 29, the BiCMIS logic circuit shown in FIG. 27 has lost its availability as a high-speed logic when the power supply potential is about 4.0 V or less.
The main reason of the deterioration of the high speed operation is as follows. When the power supply potential is reduced, a source-drain potential Vds of an N-channel MIS transistor (hereinafter referred to as NMIS) 2705 is also reduced since a base-emitter potential Vbe of a bipolar transistor (hereinafter referred to as BJT) is constant. For this reason, a base current of the BJT 2702 is abruptly reduced.
FIG. 30 shows a circuit disclosed in U.S. Pat. No. 4,558,234. In this circuit, BJT 3001 and NMIS 3002 are used for a pull-up and a pull-down of the output, respectively. This circuit uses the NMIS as the pull-down transistor and therefore does not exhibit the abrupt deterioration of the speed even in the neighborhood of 3 V of the power supply potential. However, the use of the NMIS as the pull-down transistor will increase the delay of the negative-going output signal when driving a load having a large capacitance. The increase of the conductance of the NMIS for improving the driving capability will increase the gate capacitance of the NMIS and deteriorate the speed of the circuit in the upstream. Further, there is a signal-delay due to drain-junction capacitance.
The reduction of the power supply potential for the LSIs is not avoidable from a view point of solving problems of reduced potential-resistivity of a refined semiconductor device and increased power dissipation due to high integration. For this reason, the BiCMIS logic circuit which can exhibit a high performance as in the prior art even with the low power supply potential has been desired.
However, according to the conventional BiCMIS described above, the reduction of the power supply potential in the neighborhood of 3 V will abruptly deteriorate the switching speed. For this reason, the conventional BiCMIS cannot be used as the high-speed logic circuit in the next generation.